Many devices now require low drop out regulators (LDO's) that have stability at very low capacitive loads (1 μF typical) . This is attractive for reducing the costs of external components and board area. Also, devices require low dropout voltages and very low power consumption for battery-operated applications.
These requirements force LDO designers to use Miller compensated PMOS LDO's with quiescent current boosting techniques. This is because the output capacitor is no longer large enough to produce a large enough dominant pole and quiescent current boosting (dependent on sensed output current) is required in order to save current during light load conditions and meet transient performance requirements. Transient voltage dip requirement, resulting from sudden load current changes, are more difficult to meet as the load capacitor is reduced.